Zone
Offerman Consulting
bookmark bookmark site
permalink permalink
mail mail
Share on Twitter Share on Facebook Share on LinkedIn spacer Follow me on Twitter Find me on Facebook View my profile on LinkedIn spacer Asus: Green Design
spacer Zone

Testing Semiconductor Memories

An Open Notation for Memory Tests

Aad Offerman and Ad J. van de Goor: An Open Notation for Memory Tests (also available in PostScript format)
(presented at the IEEE International Workshop on Memory Technology, Design and Testing, 1997).

Cited by:

  • F. Karimi, F. Lombardi: A scan-BIST environment for testing embedded memories, Proceedings of the Eighth IEEE International On-Line Testing Workshop, 2002, Pages 211-217,
  • Karl Thaller: A Highly-Efficient Transparent Online Memory Test, Proceedings of the 2001 IEEE International Test Conference, p.230, October 30 - November 1, 2001,
  • kkamae@esrl.ssu.ac.kr: Programmable Embedded Memory BIST Using Embedded Processor,
  • culee@watt.ssu.ac.kr: Programmable BIST Architecture to find faults based on defect injection,
  • US Patent 6496950: Testing content addressable static memories,
  • US Patent 6550032: Detecting interport faults in multiport static memories,
  • US Patent 6757854: Detecting faults in dual port FIFO memories.

Aad Offerman and Ad J. van de Goor: An Open Notation for Memory Tests (also available in PostScript format)
(Technical Report No.1-68340-44(1997)07, Delft University of Technology)

This paper contains the description of a language that was intended to be open, and at the same time handle most of the tests used these days. The result might be a little overwhelming.

We have realized that building and building on top of this open notation is not the way to go in the long run, and are thinking about better solutions at the moment. The next step will probably be a language that looks more like a general programming language providing facilities commonly used in memory tests. Furthermore, it is tempting to try to design notations for the specification of faults and for memory architectures at the same time, and make good use of the fact that the three of them are so closely related. However, this only exists in our heads yet, so no paper on this can be provided at the moment.

Towards a Uniform Notation for Memory Tests

Ad J. van de Goor, Aad Offerman, and Ivo Schanstra: Towards a Uniform Notation for Memory Tests (also available in PostScript format)
(presented at the European Design & Test Conference and Exhibition 96)

Cited by:

  • Chauchin Su, Shih-Ching Hsiao, Hau-Zen Zhau, Chung-Len Lee: A computer aided engineering system for memory BIST; Proceedings of the 2001 conference on Asia South Pacific design automation, p.492-495, January 2001, Yokohama, Japan,
  • A.P. Zankovich, V.N. Yarmolik: Nondestructive RAM Testing by Analyzing the Output Data for Symmetry, Automation and Remote Control, v.64 n.9, p.1488-1500, September 2003.

In here you can find a predecessor to the language above that is much more limited (more like an extension to the March test notation) and thus much more cleaner.
For this language a lex & yacc front-end is available.

Thesis Project: Automatic Memory Test Verification and Generation

Abstract

Designing memory tests which are complete and irredundant is hard to do. It is difficult to verify whether a certain test indeed covers all faults it is designed for (verification for completeness), and if it contains elements that can be left out without affecting its completeness (verification for irredundancy).

Therefore, a method is presented to automatically verify the completeness and irredundancy of memory tests. This method includes the definition of a two-dimensional memory model that determines the abstraction level, and the specification of memory characteristics, memory faults, and memory tests.

In the fault specification, a great variety of memory cell array faults and port faults can be specified. There is a strict separation between the behaviour of the fault, and the layout in the memory. Furthermore, the use of natural defaults allows the user to work only at an abstraction level as deep as needed.

To specify memory tests, a new memory test language has been designed. The widely used standard march test language is a natural subset of this memory test language. Furthermore, the memory test language has a much wider applicability than only this specific application; it can be practized for others too.

The presented method has been implemented in the programming language C++ for the UNIX platform and the X Window System grafical user interface. Several interpreters for the memory test language were implemented using the standard UNIX tools lex and yacc.

The complete thesis report (237 pages, in PostScript format).